1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit for finely regulating reference voltage.
2. Related Art
In general, a semiconductor memory apparatus receives power supply voltages, such as an external power supply voltage VDD and a ground power supply voltage VSS, and generates and uses internal voltages, such as a reference voltage Vref, a peripheral voltage Vperi, a core voltage Vcore, a boost voltage VPP, and a substrate bias voltage VBB. Typically, voltage generating circuits that generate internal voltages are included in the semiconductor memory apparatus. Alternatively, the reference voltage Vref can be provided from the outside through a pad. The reference voltage Vref is mainly used to provide a reference for discriminating the logic value of a signal in a data input buffer.
Referring to FIG. 1, a conventional semiconductor integrated circuit includes a reference voltage pad 10, and first to n-th input buffers 20-<1:n> (where n is a natural number).
The reference voltage pad 10 receives an external reference voltage evref and supplies the external reference voltage evref to the first to n-th input buffers 20-<1:n>. The first to n-th input buffers 20-<1:n> buffer data by using the external reference voltage evref.
The external reference voltage evref needs to be maintained at a predetermined level. However, an increase in swing speed of signals that are received by the semiconductor integrated circuit may cause an increase in power consumption. Then, power noise may occur and accordingly the level of the external reference voltage evref may be changed. If power noise occurs, the levels of voltages output from the first to n-th input buffers 20-<1:n> may be distorted due to noise. If the level of the reference voltage to be internally used is distorted, an error may occur in the operation to discriminate the logic value of a signal. In addition, the change in the level of the reference voltage may lead to a change in the setup/hold time of the signal. For this reason, the operation stability of the semiconductor integrated circuit may be deteriorated.